I set up a DLN-2 to talk to an I2C slave on a DUT. The SCL/SDA signals exiting the Diolan are incorrect--the data changes on the falling edge of SCL. This essentially means the hold time or the setup time is zero. These outputs do not align with Diolan's theory website. Need to understand if this is a faulty chip, or hidden jumper setting that can be engaged.
Here is a scope shot of the output: