Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor.
All the devices connected to the I2C bus must have an open-drain (or open-collector) output stages – they can either pull the bus low or be in high-impedance. When there is no data transmission on the I2C bus, both lines are HIGH. In this case, we say that the I2C bus is free.
I2C master generates clock signal on the SCL line. One SCL pulse is generated for each data bit. The data on the SDA line must be stable during the HIGH period of the clock (while SCL line is high). The changes on the SDA line occur when the SCL line is LOW. The only exception from this rule are START, STOP and Repeated START Conditions described later.