I2C is a two-wired serial bus developed by Philips (now NXP) in the early '80s. Currently, the I2C bus is widely used for interconnection of single-chip microcontrollers, memory chips (EEPROM), analogue-to-digital and digital-to-analog converters, pressure and temperature sensors as well as a variety of other peripheral devices.
I2C bus specification describes four operating speed categories for bidirectional data transfer:
|Standard-mode (Sm)||a bit rate up to 100 kbit/s|
|Fast-mode (Fm)||a bit rate up to 400 kbit/s|
|Fast-mode Plus (Fm+)||a bit rate up to 1 Mbit/s|
|High-speed mode (Hs-mode)||a bit rate up to 3.4 Mbit/s|
I2C bus uses two lines - SDA (data line) and SCL (clock line).
The data is transmitted between two devices - Master and Slave. Master initiates data transfer and generates the synchronization signals. Slave begins data transmission only after master requests it.
Multiple master and slave devices can be connected to the same bus. Later we will discuss the role of each of them, but now it is important to understand how they can transmit data on the same wire, avoiding conflicts.
All devices are connected to the bus via an open collector or open drain. With this connection, the device may output either a logic zero or nothing at all (the output is in the high impedance state).
If outputs of all connected devices are in the high-impedance state, the two external pull-up resistors Rp will hold the lines at high voltage level (logic 1 state). A typical value for these resistors ranges from 1 K to 10 K.
If one or more devices output logic 0, they set the line voltage to low level. The bus is considered to be free when no transmission happens and both lines are in the logic 1 state.
In later chapters, we will examine in detail a variety of options for connecting devices to the I2C bus. Now let's move on and study the I2C protocol by the example of one data byte transmission from the I2C bus master to the slave.
This waveform can be divided into seven parts:
- generation of the START (S) condition
- transmission of the slave device address (0x51)
- data direction bit (read or write)
- acknowledgment (ACK) of the slave device address
- transmission of the data byte
- acknowledgment (ACK) of the data byte
- generation of the STOP (P) condition
We will discuss all seven parts of this waveform in I2C Byte Transfer section. Now lets turn our attention to the transmission of one data bit by the I2C bus.
While transferring data, values on the SDA line are changed when the SCL line is LOW. When the SCL line is HIGH, the receiver reads the data bit (the state of the SDA line). At this point the value of the SDA line must be stable.