I2C Byte Transfer

Let’s examine the waveform of transaction where I2C Master transmits one byte of data to the I2C Slave device.

As we saw in the previous section, the data on the SDA line can be changed when the clock signal on the SCL line is LOW. Exceptions for this rule are START and STOP conditions.  There is also a repeated START (Sr) condition, but it will be discussed later.

START condition (S) notifies the Slaves on the transaction beginning. To generate a START condition, the master changes the SDA line from one to zero leaving the SCL line HIGH. After that the Master outputs zero on the SCL line to prepare the bus for transmission of the first bit.

The first seven bits, which follow after START condition, contain I2C slave address. As any other data, the address is transmitted sequentially, starting with the most significant bit (MSB) and ending with the least significant bit (LSB). Each Slave device, which is connected to the I2C bus, must have a unique address. This transaction involves the device with address 1010001 (0x51). All other slaves wait for the STOP condition.

The eighth bit of the first byte defines the direction of transmission. In our case, it is set to zero. This means that the data is transmitted from the Master to the Slave (the write operation). The direction of transmission is set by the Master.

Every eight bits of data (including the address and transmission direction byte) must be followed by the acknowledge bit (ACK). This bit is set by the receiver. In our case, the byte was transferred by the Master, so the Slave sets the acknowledge bit to 0. The Master generates the clock pulse for the acknowledge bit (as well as all the other clocks).   

There are three cases when the address byte is not acknowledged (high level on the SDA line):

1. The Slave device with this address is not connected to the bus.
2. The Slave does not support this transfer direction (write in our case). There are a number of devices that support only read operations. For example, some temperature and pressure sensors.
3. The Slave is currently busy with processing of previous command and it is not ready to receive the new one. In some cases the Acknowledge can be delayed by the Slave by holding the SCL line at zero. But we'll discuss this in the synchronization section.

Regardless of the lack of acknowledgment reasons, the Master must generate a STOP condition and free the bus.

After acknowledgment of the address byte, the Master can transmit the first data byte. The data byte must be acknowledged by the Slave as well.

When the transmission is finished, the Master generates a STOP condition and releases the bus. STOP condition is generated by the change of the SDA line from low to high while the SCL line is high. To prepare for the STOP condition, the Master must set the SDA line to zero during the low phase of the clock. 

Let’s examine the waveform of transaction where I2C Master transmits one byte of data to the I2C Slave device.

As we saw in the previous section, the data on the SDA line can be changed when the clock signal on the SCL line is LOW. Exceptions for this rule are START and STOP conditions.  There is also a repeated START (Sr) condition, but it will be discussed later.

START condition (S) notifies the Slaves on the transaction beginning. To generate a START condition, the master changes the SDA line from one to zero leaving the SCL line HIGH. After that the Master outputs zero on the SCL line to prepare the bus for transmission of the first bit.

The first seven bits, which follow after START condition, contain I2C slave address. As any other data, the address is transmitted sequentially, starting with the most significant bit (MSB) and ending with the least significant bit (LSB). Each Slave device, which is connected to the I2C bus, must have a unique address. This transaction involves the device with address 1010001 (0x51). All other slaves wait for the STOP condition.

The eighth bit of the first byte defines the direction of transmission. In our case, it is set to zero. This means that the data is transmitted from the Master to the Slave (the write operation). The direction of transmission is set by the Master.

Every eight bits of data (including the address and transmission direction byte) must be followed by the acknowledge bit (ACK). This bit is set by the receiver. In our case, the byte was transferred by the Master, so the Slave sets the acknowledge bit to 0. The Master generates the clock pulse for the acknowledge bit (as well as all the other clocks).   

There are three cases when the address byte is not acknowledged (high level on the SDA line):

1. The Slave device with this address is not connected to the bus.
2. The Slave does not support this transfer direction (write in our case). There are a number of devices that support only read operations. For example, some temperature and pressure sensors.
3. The Slave is currently busy with processing of previous command and it is not ready to receive the new one. In some cases the Acknowledge can be delayed by the Slave by holding the SCL line at zero. But we'll discuss this in the synchronization section.

Regardless of the lack of acknowledgment reasons, the Master must generate a STOP condition and free the bus.

After acknowledgment of the address byte, the Master can transmit the first data byte. The data byte must be acknowledged by the Slave as well.

When the transmission is finished, the Master generates a STOP condition and releases the bus. STOP condition is generated by the change of the SDA line from low to high while the SCL line is high. To prepare for the STOP condition, the Master must set the SDA line to zero during the low phase of the clock.