SPI bus can operate at very high speeds, which may be too fast for some slave devices. To accommodate such devices, the SPI bus contains the clock (CLK). The signal on the SCK line is transmitted with the same frequency as data flows. Thus, there is no need to synchronize the transmission speed of master and slave devices.
To configure the clock signal of the master, use the DlnSpiMasterSetFrequency() function.
When configuring the SPI master interface, you specify the frequency value supported by the slave device. If the specified value is not compatible with your DLN adapter, the function approximates the value to the closest lower frequency value supported by the adapter.
A range of supported clock frequency values depends on the DLN adapter:
DLN-1 adapters support clock frequency from 2kHz up to 4MHz.
DLN-2 adapters support clock frequency from 2kHz up to 18MHz.
DLN-4 adapters support clock frequency from 376kHz up to 48MHz.
In addition to setting the clock frequency, the master also configures the clock polarity (CPOL) and clock phase (CPHA). For detailed information, read Clock Phase and Polarity.