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Clock Stretching

In an I2C communication, a master device determines the clock speed. The I2C bus provides an explicit clock signal that relieves a master and a slave from synchronizing exactly to a predefined baud rate.However, some slave devices may receive or transmit bytes of data at a fast rate, but need more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW to force the master into a wait-state until the slave is ready for the next byte transmission. This mechanism is called clock stretching. An I2C slave is allowed to hold the SCL line LOW if it needs to reduce the bus speed. The master on the other hand is required to read back the SCL signal after releasing it to the HIGH state and wait until the SCL line has actually gone HIGH. DLN-series adapters support clock stretching. Taking into consideration the impacts of clock stretching, the total speed of the I2C bus might be significantly decreased.

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